Western Digital revealed work on 162-layer BiCS6 flash memory and plans to create memory with more than 200 layers

Western Digital this week revealed its plans for 3D NAND memory in the coming years.
The company said it is working with its Japanese partner Kioxia to develop smaller-area, 162-layer Flash memory chips and flash memory with more than 200 layers of capacity.Image source: Western DigitalThe next-generation BiCS6 3D NAND chip will arrive later this year.
At first glance it will not be the most advanced chips by the number of vertical layers - only 162 layers, which against the background of just presented Micron 232-layer 3D NAND chips looks pretty modest.
Nevertheless, the capacity of WD and Micron's solutions is the same - 128 GB (1 Tb).
The area of BiCS6 is the most compact in the industry of 68 mm2.
The company was able to achieve this by significantly reducing the physical size of memory cells, which helped to use a new material in their structure.
BiCS6 memory will store four bits per cell (QLC).
Reducing the physical volume of the cell with a combination of writing four bits to each cell should lead to a reduction in the number of overwrite cycles, but WD has not yet disclosed this value.
At the same time, the speed of BiCS6 memory promises to be 60 percent faster than current solutions, allowing it to be used both for mass-market drives and high-capacity server SSDs.
Increased density should also reduce the cost of production, which is important for everyone.Image source: Western Digital Another new development looks equally interesting - BiCS+ memory with more than 200 layers.
It is claimed that it is being developed from scratch mainly for server SSDs.
BiCS+ memory will appear by 2024 and will provide up to 55% increase in bits per wafer compared to BiCS6 memory, as well as speed increase of up to 60%.
WD expects to see a 15 percent increase in write speeds, which is as important as anything else for NAND flash memory.Image source: Western DigitalWD is like other 3D NAND manufacturers, with the goal of having 500 or more layers of 3D NAND in the future.
Produce such memory is only possible through a combination of multiple technologies, including vertical \"gluing\" of memory crystals.
The company does not lose hope to release memory with writing five bits in each cell (PLC), but it is no less difficult than releasing 3D NAND with 500 layers, which puts off the time of its appearance.